1. Field of Disclosure
The present disclosure relates to three-dimensional integrated circuit. More particularly, the present disclosure relates to a through-silicon via self-routing circuit and a routing method' thereof.
2. Description of Related Art
As the people's need and the requirement to the electronic technology are increasing, intelligent electronics IE) draws more and more attention from global everywhere. To follow the more and more rigorous standard for integrated circuit (IC), and to achieve higher speed, lower power, smaller size, and bigger storage, three-dimensional (3D) IC is the main approach for this field.
Among the filed of IE, memory is not only the essential component for 3C products or automotive electronics, but also the indispensable component for biomedical electronics. As the scale of data and intelligence grows larger and larger rapidly, the storage requirement for memory thus grows bigger and bigger quickly.
On the other hand, memory is also suit for adopting 3D IC. In the fierce competition of 3D IC market, Micron Technology, Inc. developed Hybrid Memory Cube (HMC), and HMC turns into the brand new structure of memory development. The efficiency of saving energy under HMC structure can be 7 times the modern third generation of double-data-rate three dynamic random access memory (DDR3-DRAM). The concept of HMC is to employ a configuration of vertical stack-based memory allocation, to form a micro-cube chip. HMC also employs an innovative high-speed interface to build a new standard of energy saving efficiency in data transfer, and the transfer speed can as achieve the level of 1 terabit per second. The development of HMC can greatly improve the development of the cloud computing servers, ultra-book laptops, televisions, tablet computers, and smart phones.
On December 2010, Samsung Electronics Co., Ltd. also announced its 8 GB DDR3-DRAM module developed by 3D chip stacking technology, which is also referred to as through silicon via (TSV). The 8 GB DDR3-DRAM module consisted of two 4 GB chips. Samsung Electronics Co., Ltd. again announced its 32 GB DDR3-DRAM module developed by TSV on August 2011. On 6 Dec. 2011, Taiwan's Industrial Technology Research Institute (ITRI) and Intel Corporation signed an agreement to jointly develop next-generation memory devices. In view of the above, memory devices with high yield rate and high energy-efficiency is very important to the future world. However, there are still many difficulties regarding 3D IC development. For instance, the yield rate of memory is generally around 20%, which is not good. The yield rates of silicon interposer and TSV are not good either.
3D IC is a chip in which multiple tiers of active electronic components are integrated into a single circuit, by thinning, bonding, and TSVs, to turn conventional 2D planar chip into the form of 3D stack. Before the complete 3D IC technique is presented to the public, there are many manufacturing technologies in the prior art, such as Package on Package (PoP), Multi-Chip Package (MCP), and 2.5D stacks for being between 2D chips and 3D chip stacks. Therefore, the TSV interconnection between two tiers can be achieved through several TSVs, flip-chip bumps, micro-bumps, interposers, or package bumps. Before further introducing TSV Redundancy Analysis, a principle is to generally adopted and should be stated: Two adjacent tiers are simplified as a TSV, and every TSV among a vertical lead can be repaired separately.
Recent implementations for TSV Redundancy Analysis are mostly done by switching circuits. Some technologies are described as below.
Crossbar-based 3D Network: As shown in FIG. 1A, a conventional M-to-N crossbar switch network can completely select N paths from M TSVs with at most M-N defected TSVs but it is usually utilized in a small group due to switch overhead in O(MN) and high branch effort in O(N). In 2006 1st International Conference on Nano-Networks, Nomura, K., et al. thus published ‘Novel design of three-dimensional crossbar for future network on chip based on post-silicon devices,’ (Nomura, K., et al.: ‘Novel design of three-dimensional crossbar for future network on chip based on post-silicon devices’. Int. Conf. Nano-Networks, Lausanne, Switzerland, 2006) provided a strategy of grouping TSVs.
Neighbor-Shift Scheme: To avoid multiple switching causing TSV signal delay, Laisne, M., Arabi, K., and Petrov, T issued a US patent of ‘Systems and Methods Utilizing Redundancy in Semiconductor Chip Interconnects,’ (Laisne, M., Arabi, K., and Petrov, T.: ‘Systems and Methods Utilizing Redundancy in Semiconductor Chip Interconnects’, U.S. Patent 61/095,855, Sep. 10, 2008) providing a neighbor-shift manner as shown in FIG. 1B. The benefit for this approach is that only two switching delay are required between two tiers. The downside, however, is that only one single TSV fault is repairable.
Micro-Networking: In 2010, Contreras, A. A., Moon, T. K Dasu, A., and Gunther, J. H. published a paper of ‘Micronetworking: reliable communication on 3D integrated circuits’ (Contreras, A. A. Moon, T. K., Dasu, A., and Gunther, J. H.: ‘Micronetworking: reliable communication on 3D integrated circuits’, Electron. Lett., 2010, 46, (4), pp. 291-293). For a given example shown in FIG. 1C, while there are k=4 tracks needed for every tier, a switching box as shown in FIG. 5d is required. And there are 18 transmission gates needed for the switching box of FIG. 5d. In the worst case, the routing passes 4(M-1)+2k transmission gates, and there are 2k transmission gates needed. The micronetworking compromises the area overhead and the fault multiplicity but only 2k faulty TSVs can be repaired from M TSVs in the worst case, when the micronetworking is constructed with k tracks and (4k+2) M switches per tier.
On the other hand, in 2010, Hsieh, k-C., and Hwang, T. published another paper of ‘TSV redundancy: architecture and design issues in 3D IC.’ (Hsieh, A.-C., and Hwang, T.: ‘TSV redundancy: architecture and design issues in 3D IC’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, 20, (4), pp. 711-722). In this paper, Neighbor-Shift Scheme can be modified into TSV Chain, which can be considered as a special case whereas k=1.
Every conventional technology has its own view and theory about the repair rate of TSVs, since adopting different fault calculating model. The repair rate of single-TSV fault of all above mentioned technologies are 100%. But if there are more than one single TSV fault occurred, the repair rate of Neighbor-Shift Scheme is 0%, while the repair rate of Micro-Networking can be 100% if the number of defected TSVs F<2k, and the repair rate of Crossbar-based 3D Network can be 100% if the number of defected TSVs F≦(M-N). Neighbor-Shift Scheme technology would be no use if the number of defected TSVs is more than one. Micro-Networking and Crossbar-based 3D to Network technologies can repair multiple defected TSVs. However, the routing control for Micro-Networking or Crossbar-based 3D Network is difficult to integrated with 3D IC design and test flow, so that the design and production costs for adopting these technologies are high.